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1 ? fn6424.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. copyright intersil americas inc. 2007, 2010. all rights reserved 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcpis a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. isl22414 single digitally controlled potentiometer (xdcp?) low noise, low power, spi ? bus, 256 taps the isl22414 integrates a si ngle digitally controlled potentiometer (dcp), control logic and non-volatile memory on a monolithic cmos integrated circuit. the digitally controlled potentio meter is implemented with a combination of resistor el ements and cmos switches. the position of the wiper is controll ed by the user through the spi serial interface. the potentiometer has an associated volatile wiper register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr control the position of the wiper. at power-up the device recalls the contents of the dcp?s ivr to the wr. the isl22414 also has 14 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. the isl22414 features a dual supply that is beneficial for applications requiring a bipolar range for dcp terminals between v- and vcc. the dcp can be used as three-te rminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? 256 resistor taps ? spi serial interface with write/read capability ? daisy chain configuration ? shutdown mode ? non-volatile eeprom stor age of wiper position ? 14 general purpose non-volatile registers ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t + 55c ? wiper resistance: 70 typical @ 1ma ? standby current <2.5a max ? shutdown current <2.5a max ? dual power supply - vcc = 2.25v to 5.5v - v- = -2.25v to -5.5v ?10k , 50k or 100k total resistance ? extended industrial temperature range: -40c to +125c ? military temperature range: -55 to +125c ? 10 lead msop ? pb-free (rohs compliant) pinout isl22414 (10 ld msop) top view 1 2 3 4 5 6 10 9 8 7 sdo v- cs sdi vcc sck gnd rl rw rh o ordering information part number (notes 1, 2) part marking resistance option (k ) temp. range (c) package (pb-free) pkg. dwg. # isl22414tfu10z 414tz 100 -40 to +125 10 ld msop m10.118 isl22414ufu10z 414uz 50 -40 to +125 10 ld msop m10.118 ISL22414WFU10Z 414wz 10 -40 to +125 10 ld msop m10.118 isl22414wmu10z 414wm 10 -55 to +125 10 ld msop m10.118 notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. 2. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. data sheet december 16, 2010
2 fn6424.1 december 16, 2010 block diagram spi interface vcc rh gnd rl rw sck sdo sdi cs power up interface, control and status logic non-volatile registers v- wr volatile register and wiper control circuitry pin descriptions msop pin symbol description 1 sck spi interface clock input 2 sdo data output of the spi serial interface 3 sdi data input of the spi serial interface 4cs chip select active low input 5 v- negative power supply pin 6 gnd device ground pin 7 rl ?low? terminal of dcp 8 rw ?wiper? terminal of dcp 9 rh ?high? terminal of dcp 10 vcc power supply pin isl22414
3 fn6424.1 december 16, 2010 absolute maximum rati ngs thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to 0.3v voltage at any dcp pin with respect to gnd . . . . . . . . . . v- to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup . . . . . . . . . . . . . . . . . . . . . . . . . class ii, level a @ +125c esd human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400v thermal resistance (typical, note 3) ja (c/w) 10 lead msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 maximum junction temperature (pla stic package). . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range full industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mw v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 5.5v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25v to -5.5v max wiper current iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. analog specifications over recommended operating conditi ons unless otherwise stated. boldface limits apply over the operating temperature range. symbol parameter test conditions min (note 18) typ (note 4) max (note 18) unit r total rh to rl resistance w option 10 k u option 50 k t option 100 k rh to rl resistance tolerance -20 +20 % end-to-end temperature coefficient w option 150 ppm/c u, t option 50 ppm/c v rh , v rl dcp terminal voltage v rh and v rl to gnd v- v cc v r w wiper resistance rh - floating, v rl = v-, force iw current to the wiper, i w = (v cc - v rl )/r total 70 250 c h /c l /c w potentiometer capacitance see ?dcp macro model? on page 7 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pin from v- to v cc -1 0.1 1 a voltage divider mode (v- @ rl; v cc @ rh; measured at rw, unloaded) inl (note 9) integral non-linearity monotonic over all tap positions w option -1.5 0.5 1.5 lsb (note 5) u, t option -1.0 0.2 1.0 lsb (note 5) dnl (note 8) differential non-linearity monotonic over all tap positions w option -1.0 0.4 1.0 lsb (note 5) u, t option -0.5 0.15 0.5 lsb (note 5) zserror (note 6) zero-scale error w option 0 1 5 lsb (note 5) u, t option 0 0.5 2 fserror (note 7) full-scale error w option -5 -1 0 lsb (note 5) u, t option -2 -1 0 tc v (note 10) ratiometric temperature coefficient dcp register set to 80 hex 4 ppm/c isl22414
4 fn6424.1 december 16, 2010 f cutoff -3db cut off frequency wiper at midpoint (80hex) w option (10k) 1000 khz wiper at midpoint (80hex) u option (50k) 250 khz wiper at midpoint (80hex) t option (100k) 120 khz resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 14) integral non-linearity w option -3 1.5 3 mi (note 11) u, t option -1 0.3 1 mi (note 11) rdnl (note 13) differential non-linearity w option -1.5 0.4 1.5 mi (note 11) u, t option -0.5 0.15 0.5 mi (note 11) roffset (note 12) offset w option 0 1 5 mi (note 11) u, t option 0 0.5 2 mi (note 11) tc r ( notes 15 ) resistance temperature coefficient dcp register set between 32 hex and ff hex 50 ppm/c analog specifications over recommended operating conditi ons unless otherwise stated. boldface limits apply over the operating temperature range. (continued) symbol parameter test conditions min (note 18) typ (note 4) max (note 18) unit operating specifications over the recommended operating conditi ons unless otherwise specified. boldface limits apply over the operating temperature range. symbol parameter test conditions min (note 18) typ (note 4) max (note 18) unit i cc1 v cc supply current (volatile write/read) v cc = 5.5v, v- = 5.5v, f sck = 5mhz; (for spi active, read and volatile write states only) 0.36 1 ma v cc = 2.25v, v- = -2.25v, f sck = 5mhz; (for spi active, read and volatile write states only) 0.13 0.4 ma i v-1 v- supply current (volatile write/read) v- = -5.5v, v cc = 5.5v, f sck = 5mhz; (for spi active, read and volatile write states only) -1 -0.18 ma v- = -2.25v, v cc = 2.25v, f sck = 5mhz; (for spi active, read and volatile write states only) -0.4 -0.06 ma i cc2 v cc supply current (non-volatile write/read) v cc = 5.5v, v- = 5.5v, f sck = 5mhz; (for spi active, read and non-volatile write states only) 1 2 ma v cc = 2.25v, v- = -2.25v, f sck = 5mhz; (for spi active, read and non-volatile write states only) 0.3 0.7 ma i v-2 v- supply current (non-volatile write/read) v- = -5.5v, v cc = 5.5v, f sck = 5mhz; (for spi active, read and non-volatile write states only) -2 -1.2 ma v- supply current (non-volatile write/read) v- = -2.25v, v cc = 2.25v, f sck = 5mhz; (for spi active, read and non-volatile write states only) -0.7 -0.4 ma i sb v cc current (standby) v cc = +5.5v, v- = -5.5v @ +85c, spi interface in standby state 0.2 1.5 a v cc = +5.5v, v- = -5.5v @ +125c, spi interface in standby state 12.5a v cc = +2.25v, v- = -2.25v @ +85c, spi interface in standby state 0.1 1 a v cc = +2.25v, v- = -2.25v @ +125c, spi interface in standby state 0.5 2 a isl22414
5 fn6424.1 december 16, 2010 i v-sb v- current (standby) v- = -5.5v, v cc = +5.5v @ +85c, spi interface in standby state -2.5 -0.7 a v- = -5.5v, v cc = +5.5v @ +125c, spi interface in standby state -4 -3 a v- = -2.25v, v cc = +2.25v @ +85c, spi interface in standby state -1.5 -0.3 a v- = -2.25v, v cc = +2.25v @ +125c, spi interface in standby state -3 -1 a i sd v cc current (shutdown) v cc = +5.5v, v- = -5.5v @ +85c, spi interface in standby state 0.2 1.5 a v cc = +5.5v, v- = -5.5v @ +125c, spi interface in standby state 12.5a v cc = +2.25v, v- = -2.25v @ +85c, spi interface in standby state 0.1 1 a v cc = +2.25v, v- = -2.25v @ +125c, spi interface in standby state 0.5 2 a i v-sd v- current (shutdown) v- = -5.5v, v cc = +5.5v @ +85c, spi interface in standby state -2.5 -0.7 a v- = -5.5v, v cc = +5.5v @ +125c, spi interface in standby state -4 -3 a v- = -2.25v, v cc = +2.25v @ +85c, spi interface in standby state -1.5 -0.3 a v- = -2.25v, v cc = +2.25v @ +125c, spi interface in standby state -3 -1 a i lkgdig leakage current, at pins sck, sdi, sdo and cs voltage at pin from gnd to v cc -0.5 0.5 a t wrt dcp wiper response time cs rising edge to wiper new position 1.5 s t shdnrec dcp recall time from shutdown mode cs rising edge to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 1.9 2.1 v vccramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and spi interface in standby state 5 ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t + 55oc 50 years t wc (note 16) non-volatile write cycle time 12 20 ms serial interface specifications v il sck, sdi, and cs input buffer low voltage -0.3 0.3*v cc v v ih sck, sdi, and cs input buffer high voltage 0.7*v cc v cc +0.3 v hysteresis sck, sdi, and cs input buffer hysteresis 0.05*v cc v v ol sdo output buffer low voltage i ol = 4ma for open drain output, pull-up voltage vpu = v cc 00.4 v operating specifications over the recommended operating conditi ons unless otherwise specified. boldface limits apply over the operating temperature range. (continued) symbol parameter test conditions min (note 18) typ (note 4) max (note 18) unit isl22414
6 fn6424.1 december 16, 2010 r pu (note 17) sdo pull-up resistor off-chip maximum is determined by t ro and t fo with maximum bus load cb = 30pf, f sck = 5mhz 2 k cpin sck, sdi, sdo and cs pin capacitance 10 pf f sck spi frequency 5 mhz t cyc spi clock cycle time 200 ns t wh spi clock high time 100 ns t wl spi clock low time 100 ns t lead lead time 250 ns t lag lag time 250 ns t su sdi, sck and cs input setup time 50 ns t h sdi, sck and cs input hold time 50 ns t ri sdi, sck and cs input rise time 10 ns t fi sdi, sck and cs input fall time 10 20 ns t dis sdo output disable time 0 100 ns t so sdo output setup time 50 ns t v sdo output valid time 150 ns t ho sdo output hold time 0 ns t ro sdo output rise time r pu = 2k, cbus = 30pf 60 ns t fo sdo output fall time r pu = 2k, cbus = 30pf 60 ns t cs cs deselect time 2 s notes: 4. typical values are for t a = +25c and 3.3v supply voltage. 5. lsb: [v(rw) 255 ? v(rw) 0 ] / 255. v(rw) 255 and v(rw) 0 are v(rw) for the dcp register set to ff hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 6. zs error = v(rw) 0 / lsb. 7. fs error = [v(rw) 255 ? v cc ] / lsb. 8. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 255. i is the dcp register setting. 9. inl = [v(rw) i ? i ? lsb ? v(rw)]/lsb for i = 1 to 255 10. for i = 16 to 255 decimal, t = -40c to +125c or t = -55c to +125c. max( ) is the maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage over the temperature range. 11. mi = | rw 255 ? rw 0 | / 255. mi is a minimum increment. rw 255 and rw 0 are the measured resistances for t he dcp register set to ff hex and 00 hex respectively. 12. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 255 / mi, when measuring between rw and rh. 13. rdnl = (rw i ? rw i-1 ) / mi -1, for i = 1 to 255. 14. rinl = [rw i ? (mi ? i) ? rw 0 ] / mi, for i = 1 to 255. 15. for i = 16 to 255, t = -40c to +125c or t = -55c to +125c. max( ) is the maximum value of the resistance and min( ) is the minimum value of the resistance over the temperature range. 16. t wc is the time from the end of a write sequence of spi serial inte rface, to the end of the self-timed internal non-volatile write cycle. 17. r pu is specified for the highest data rate transfer for the device. higher value pull-up can be used at lower data rates. 18. compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. operating specifications over the recommended operating conditi ons unless otherwise specified. boldface limits apply over the operating temperature range. (continued) symbol parameter test conditions min (note 18) typ (note 4) max (note 18) unit tc v max v rw () i () min v rw () i () ? max v rw () i () min v rw () i () + [] 2 ? --------------------------------------------------------------------------------------------- - 10 6 t c -------------- - = tc r max ri () min ri () ? [] max ri () min ri () + [] 2 ? --------------------------------------------------------------- - 10 6 t c -------------- - = isl22414
7 fn6424.1 december 16, 2010 dcp macro model timing diagrams input timing output timing xdcp timing (for all load instructions) 10pf rh r total c h 25pf c w c l 10pf rw rl ... cs sck sdi sdo msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck sdo sdi addr msb lsb t dis t ho t v ... t so ... cs sck sdi msb lsb v w t wrt ... sdo high impedance isl22414
8 fn6424.1 december 16, 2010 typical performance curves figure 1. wiper resistance vs tap position [ i(rw) = v cc /r total ] for 10k (w) figure 2. standby i cc and i v- vs temperature figure 3. dnl vs tap position in voltage divider mode for 10k (w) figure 4. inl vs tap position in voltage divider mode for 10k (w) figure 5. zs error vs temperature figure 6. fs error vs temperature 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 tap position (decimal) wiper resistance ( ) t = +25oc t = -40oc t = +125oc -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -40 0 40 80 120 temperature (c) standby current (a) i cc i v- -0.50 -0.25 0 0.25 0.50 0 50 100 150 200 250 tap position (decimal) dnl (lsb) t = +25oc v cc = 2.25v v cc = 5.5v -0.50 -0.25 0 0.25 0.50 0 50 100 150 200 250 tap position (decimal) inl (lsb) t = +25oc v cc = 5.5v v cc = 2.25v 0 0.4 0.8 1.2 1.6 2.0 -40 0 40 80 120 temperature (oc) zs error (lsb) v cc = 2.25v v cc = 5.5v 50k 10k -5 -4 -3 -2 -1 0 -40 0 40 80 120 temperature (oc) fs error (lsb) v cc = 5.5v 10k 50k v cc = 2.25v isl22414
9 fn6424.1 december 16, 2010 figure 7. dnl vs tap position in rheostat mode for 10k (w) figure 8. inl vs tap position in rheostat mode for 10k (w) figure 9. end to end r total % change vs temperature figure 10. tc for voltag e divider mode in ppm figure 11. tc for rheostat mode in ppm figure 12. frequency response (1mhz) typical performance curves (continued) -0.50 -0.25 0 0.25 0.5 0 50 100 150 200 250 tap position (decimal) rdnl (mi) v cc = 2.25v v cc = 5.5v t = +25oc -0.5 0 0.5 1.0 1.5 2.0 0 50 100 150 200 250 tap position (decimal) rinl (mi) v cc = 5.5v t = +25oc v cc = 2.25v -0.40 0.00 0.40 0.80 1.20 1.60 -40 0 40 80 120 r total change (%) 10k 50k 5.5v 2.25v temperature (oc) 0 40 80 120 160 200 16 66 116 166 tap position (decimal) tcv (ppm/oc) 50k 10k 216 266 0 100 200 300 400 500 16 66 116 166 216 tap position (decimal) tcr (ppm/oc) 50k 10k output input wiper at mid point (position 80h) r total = 10k isl22414
10 fn6424.1 december 16, 2010 pin description potentiometer pins rh and rl the high (rh) and low (rl) terminals of the isl22414 are equivalent to the fixed terminals of a mechanical potentiometer. rh and rl are referenced to the relative position of the wiper and not t he voltage potential on the terminals. with wr set to 255 decimal, the wiper will be closest to rh, and with the wr set to 0, the wiper is closest to rl. rw rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the wr register. bus interface pins serial clock (sck) this is the serial clock input of the spi serial interface. serial data output (sdo) the sdo is a serial data output pin. during a read cycle, the data bits are shifted out on the falling edge of the serial clock sck and will be available to the master on the following rising edge of sck. the output type is configured through acr[1] bit for push- pull or open drain operation. default setting for this pin is push-pull. an external pull up resistor is required for open drain output operation. note, t he external pull up voltage not allowed beyond vcc. serial data input (sdi) the sdi is the serial data input pin for the spi interface. it receives device address, operation code, wiper address and data from the spi remote host device. the data bits are shifted in at the rising edge of the serial clock sck, while the cs input is low. chip select (cs ) cs low enables the isl22414, placing it in the active power mode. a high to low transition on cs is required prior to the start of any operation after power up. when cs is high, the isl22414 is deselected and the sdo pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. principles of operation the isl22414 is an integrated circuit incorporating one dcp with its associated registers, non-volatile memory and the spi serial interface providing direct communication between host and potentiometer and memory. the resistor array is comprised of individual resistors connected in a series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. when the device is powered down, the last value stored in ivr will be maintained in the non-volatile memory. when power is restored, the conten t of the ivr is recalled and loaded into the wr to set the wiper to the initial position. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fi xed terminals of a mechanical potentiometer (rh and rl pins). the rw pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within t he dcp is controlled by an 8-bit volatile wiper register (wr). when the wr of a dcp contains all zeroes (wr[7:0]= 00h), its wiper terminal (rw) figure 13. midscale glitch, code 7fh to 80h figure 14. large signal settling time typical performance curves (continued) scl wiper cs wiper unloaded, movement from 0h to ffh isl22414
11 fn6424.1 december 16, 2010 is closest to its ?low? terminal (rl). when the wr register of a dcp contains all ones (wr[7:0]= ffh), its wiper terminal (rw) is closest to its ?high? terminal (rh). as the value of the wr increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to rl to the closest to rh. at the same time, the resistance between rw and rl increases monotonically, while the resistance between rh and rw decreases monotonically. while the isl22414 is being powered up, the wr is reset to 80h (128 decimal), which locates rw roughly at the center between rl and rh. after the power supply voltage becomes large enough for reliable non-volatile memory reading, the wr will be reload ed with the value stored in a non-volatile initial value register (ivr). the wr and ivr can be read or written to directly using the spi serial interface as described in the following sections. memory description the isl22414 contains one non-volatile 8-bit initial value register (ivr), fourteen non-volatile 8-bit general purpose (gp) registers, volatile 8-bit wiper register (wr), and volatile 8-bit access control register (acr). the memory map of isl22414 is in table 1. the non-volatile register (ivr) at address 0, contains initial wiper position and volatile register (wr) contains current wiper position. the register at address 0fh is a read-only reserved register. information read from this register should be ignored. the non-volatile ivr and volatile wr registers are accessible with the same address. the access control register (acr) contains information and control bits described below in table 2. the vol bit (acr[7]) determi nes whether the access to wiper registers wr or initial value registers ivr. if vol bit is 0, the non-volatile ivr register is accessible. if vol bit is 1, only the volatile wr is accessible. note, value is written to ivr register al so is written to the wr. the default value of this bit is 0. the shdn bit (acr[6]) disables or enables shutdown mode. when this bit is 0, dcp is in shutdown mode, i.e. dcp is forced to end-to-end open circuit and rw is shorted to rl as shown on figure 15. default value of shdn bit is 1. setting shdn bit to 1 is returned wip er to prior to shutdown mode position. the wip bit (acr[5]) is a read-onl y bit. it indicates that non- volatile write operation is in progress. the wip bit can be read repeatedly after a non-volat ile write to determine if the write has been completed. it is impossible to write or read to the wr or acr while wip bit is 1. the sdo bit (acr[1]) configures type of sdo output pin. the default value of sdo bit is 0 for push - pull output. sdo pin can be configured as open drain output for some application. in this case, an external pull up resistor is required. see ?applications information? on page 13. spi serial interface the isl22414 supports an spi serial protocol, mode 0. the device is accessed via the sdi input and sdo output with data clocked in on the rising edge of sck, and clocked out on the falling edge of sck. cs must be low during communication with the isl22414. sck and cs lines are controlled by the host or master. the isl22414 operates only as a slave device. table 1. memory map address (hex) non-volatile volatile 10 n/a acr f reserved e general purpose n/a d general purpose n/a c general purpose n/a b general purpose n/a a general purpose n/a 9 general purpose n/a 8 general purpose n/a 7 general purpose n/a 6 general purpose n/a 5 general purpose n/a 4 general purpose n/a 3 general purpose n/a 2 general purpose n/a 1 general purpose n/a 0ivr wr table 2. access control register (acr) bit # 7654321 0 bit name vol shdn wip000sdo0 rl rw rh figure 15. dcp connection in shutdown mode isl22414
12 fn6424.1 december 16, 2010 all communication over the spi interface is conducted by sending the msb of each byte of data first. protocol conventions the spi protocol contains instruction byte followed by one or more data bytes. a valid instruction byte contains instruction as the three msbs, wit h the following five register address bits (see table 3). the next byte sent to the isl22414 is the data byte. table 3. instruction byte format table 4 contains a valid instruction set for isl22414. there are only sixteen register addresses possible for this dcp. if the [r4:r0] bits are zero, then the read or write is to either the ivr or the wr register (depends of vol bit at acr). if the [r4:r0] are 10000, then the operation is on the acr. write operation a write operation to the isl22414 is a two or more bytes operation. it requires first, the cs transition from high to low. then host send a valid instruction byte, followed by one or more data bytes to sdi pin. the host terminates the write operation by pulling the cs pin from low to high. instruction is executed on rising edge of cs . for a write to address 0, the msb of the byte at address 10h (acr[7]) determines if the data byte is to be written to volatile or both volatile and non-volatile registers. refer to ?memory description? and figure 16. note, the internal non-volatile write cycle starts with the rising edge of cs and requires up to 20ms. during non-volatile write cycle the read operation to acr register is allowed to check wip bit. read operation a read operation to the isl22414 is a four byte operation. it requires first, the cs transition from high to low. then host send a valid instruction byte, followed by ?dummy? data byte, nop instruction byte a nd another ?dummy? data byte to sdi pin. the spi host receives the instruction byte (instruction code + register address) and requested data byte from sdo pin on the rising edge of sck during third and fourth bytes respectively. the host terminates the read operation by pulling the cs pin from low to high (see figure 17). reading from the ivr will not change the wr, if its contents are different. bit # 76543210 i2 i1 i0 r4 r3 r2 r1 r0 table 4. instruction set instruction set operation i2 i1 i0 r4 r3 r2 r1 r0 0 0 0xxxxxnop 0 0 1xxxxxacr read 0 1 1xxxxxacr write 1 0 0 r4 r3 r2 r1 r0 wr, ivr, gp or acr read 1 1 0 r4 r3 r2 r1 r0 wr, ivr, gp or acr write where x means ?do not care? figure 16. two byte write sequence cs sck sdi sdo wr instruction data byte 1 3 4 5 7 8 9 10 11 12 13 14 15 16 26 addr isl22414
13 fn6424.1 december 16, 2010 applications information communicating with isl22414 communication with isl22414 pr oceeds using spi interface through the acr (address 10000b), ivr (address 00000b), wr (addresses 00000b) and general purpose registers (addresses from 00001b to 01110b). the wiper of the potentiometer is controlled by the wr register. writes and reads can be made directly to these register to control and monito r the wiper position without any non-volatile memory changes. this is done by setting msb bit at address 10000b to 1 (acr[7] = 1). the non-volatile ivr stores t he power up position of the wiper. ivr is accessible when msb bit at address 10000b is set to 0 (acr[7] = 0). writing a new value to the ivr register will set a new power up position for the wiper. also, writing to this register will load the same value into the corresponding wr as the ivr. reading from the ivr will not change the wr, if its contents are different. daisy chain co nfiguration when application needs more then one isl22414, it can communicate with all of them without additional cs lines by daisy chaining the dcps as shown on figure 18. in daisy chain configuration the sdo pin of previous chip is connected to sdi pin of the following chip, and each cs and sck pins are connected to the corresponding microcontroller pins in parallel, like regular spi interface implementation. the daisy chain configuration can also be used for simultaneous setting of multiple dcps. note, the number of daisy chained dcps is limited only by the driving capabilities of sck and cs pins of microcontroller; for larger number of spi devices buffering of sck and cs lines is required. daisy chain write operation the write operation starts by high to low transition on cs line, followed by n number of two bytes write instructions on sdi line with reversed chain access sequence: the instruction byte + data byte for the last dcp in chain is going first, as shown on figure 19, where n is a number of dcps in chain. the serial data is going through dcps from dcp0 to dcp(n-1) as foll ow: dcp0 --> dcp1 --> dcp2 --> ... --> dcp(n-1). the write instruction is executed on the rising edge of cs for all n dcps simultaneously. daisy chain read operation the read operation consists two parts: first, send read instructions (n two bytes operation) with valid address; second, read the requested data while sending nop instructions (n two bytes operation) as shown on figure 20, and figure 21. the first part starts by high to low transition on cs line, followed by n two bytes read instruction on sdi line with reversed chain access sequence: the instruction byte + dummy data byte for the last dcp in chain is going first, followed by low to high transition on cs line. the read instructions are executed dur ing second part of read sequence. it also starts by high to low transition on cs line, followed by n number of two bytes nop instructions on sdi line and low to high transition of cs . the data is read on every even byte during second part of read sequence while every odd byte contains instruction code + address from which the data is being read. wiper transition when stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/under shoot, resulting from the sudden transition from a very low impedance ?make? to a much higher impedance ?break within an extremely short period of time (<50ns). two such code transitions are efh to f0h, and 0fh to 10h. note, t hat all switching transients will settle well within the settling ti me as stated in the datasheet. a small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. it may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. figure 17. four byte read sequence cs sck sdi sdo rd addr nop rd addr read data 1 8 16 24 32 isl22414
14 fn6424.1 december 16, 2010 cs sck mosi miso cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo c dcp0 dcp1 dcp2 dcp(n-1) figure 18. daisy chain configuration n dcp in a chain cs sck sdi sdo 0 wr d c p2 wr d c p1 wr d c p0 wr d c p1 sdo 1 wr d c p2 sdo 2 wr d c p2 figure 19. daisy chain write sequence of n = 3 dcp 16 clkls 16 clks 16 clks figure 20. two byte operation cs sck sdi sdo instruction addr data in data out 1 2 10 11 12 13 14 15 16 345 67 8 9 isl22414
15 fn6424.1 december 16, 2010 cs sck sdi sdo rd dcp1 rd dcp0 nop nop nop dcp2 out dcp1 out dcp0 out rd dcp2 16 clks 16 clks 16 clks 16 clks 16 clks 16 clks figure 21. daisy chain read sequence of n = 3 dcp isl22414
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6424.1 december 16, 2010 isl22414 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02

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